Sr. Staff Verification Engineer

Define, develop and optimize comprehensive verification plans and test strategies for digital/mixed-signal IP blocks, subsystems, and full integrated circuits. Drive adoption of advanced verification methodologies, best practices and tool evaluation. Report to remote verification & design teams. Mentor junior verification engineers.

Requirements

• B.S. or M.S. in Electrical or Computer Engineering
• 8+ years of industry experience in integrated circuit design verification (DV)
• Strong analytical, synthesis and problem solving skills
• Proficiency in System Verilog as High-level Verification Language and UVM implementation
• Experience with industry leading EDA verification tools (Synopsys, Cadence, Siemens)
• Demonstration of technical leadership
• Excellent verbal and written communication skills

Benefits

• Paid Time Off
• 401k Matching
• Health Insurance
• Dental Insurance
• Vision Insurance