ASIC RTL/SoC Design Engineer

Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring robust and efficient designs. Collaborate closely with the backend team and contribute to design reviews and cross-functional discussions.

Requirements

• MS with 5+ years of experience or PhD in Electrical Engineering with emphasis on RTL/SoC/digital design
• Experience with Verilog and system Verilog
• Experience with VCS, Verdi or other industry standard tools
• Experience with pre-layout simulation and post-layout simulation
• Understanding of the design flow. Ability to work with the backend team
• Familiarity with AMBA APB AXI Protocol
• Familiarity with RISC/Arm or other core architectures
• Ability to create innovative architecture and solutions to customer requirements
• Ability to work in startup environment and work both independently and as a team player, with the ability to provide technical leadership to other members of the engineering team.

Benefits

• Medical
• Professional PTO
• 401k
• Other perks