Principal Emulation and Validation Engineer
WinMax Systems CorporationSan Jose, California, United States
Posted April 19, 2017
Full Time
About the Company
WinMax is a woman and minority-owned business providing workforce solutions, staffing, consulting, technology services, and development solutions to facilitate client growth and deliver innovative solutions.
Job Description
As a Principal Emulation and Validation Engineer, you will be responsible for synthesizing complex system on chip designs, developing system level tests, and creating reusable design blocks and verification components. You will also improve and define new verification/emulation methodologies, debug and resolve Pre/Post Silicon failures, and create and maintain emulation environment for a worldwide user community.
Requirements
- BS (EE/Electrical Engineering or CS/Computer Science) required, MS (EE or CS) preferred or equivalent
- Total engineering experience: 12+ years (BS), 9+ years (MS), 6 years (PhD) or equivalent
- Hands-on experience with Leadership qualities on driving ASIC/SoC verification flows and methodologies
- Good Knowledge in languages relevant to the ASIC verification process including Verilog, System Verilog, Tcl, iTcl, Perl, Python, Ruby, C/C++, and Unix Scripting
- Strong expertise in writing system level tests and driver using C/C++, Tcl, iTcl, Perl, and Python
