Sr. DFT Engineer

Alphawave Semi is looking for a Sr. DFT Engineer to join their DFT methodology group. The role involves developing, maintaining, and supporting flows across all company business units and projects, as well as architecting methodologies and flows for an integrated, RTL centric "shift left" DFT environment.

Requirements

• Bachelor's degree in engineering science, Electrical and Computer Engineering or Computer Science
• 5+ years of experience in complex SoC designs in RTL, DFT or FE capacity
• Vast experience with various DFT EDA tools from Tessent, SNPS and Cadence
• Good knowledge and understanding in Verilog/VHDL and SystemVerilog
• Exposure with CAD and automation
• Extensively experienced with main DFT standards such as JTAG (1149.1/1149.6/1500), iJTAG (1687) and BIST techniques (memory BIST, logic BIST, interconnect BISTs)
• Track record in integrating custom made DFT logic for complex SoCs and CoWoS designs
• Experience in SoC and IP/Block level scan insertion and ATPG, simulation of zero delay and SDF annotated test sequences
• Experience in core wrapping, pattern retargeting & packetizing ATPG techniques
• SSN knowledge is a plus
• Experience in scripting/reviewing SCAN/MBIST timing constraints
• Developing DFT rule bases and DFT-DRC checks with spyglass

Benefits

• Great Compensation Package
• Health Insurance
• Retirement Savings
• Paid Time Off
• Diversity & Inclusivity