Senior Design Verification Engineer

Senior Design Verification Engineer responsible for verification of mixed signal designs and sub-systems using leading edge verification methodologies, developing directed and constrained random test cases in System Verilog, and implementing and managing complete metric-driven System Verilog and UVM verification environments.

Requirements

• BSEE + 5 years or MSEE + 1 years Digital and/or Mixed Signal IC verification experience
• Strong written and verbal communication skills
• Strong coding, object-oriented programming, and documentation skills
• Strong System Verilog fluency in verification domain

Benefits

• Medical/Dental/Vision
• 401k Matching
• Paid Time Off
• Retirement Plan