Senior Engineer Design Verification Engineering

Support and accelerate product development of industry leading products involving behavioral modeling of analog circuits, spice, and mixed-signal verification. Establish and promote the adoption of metric-driven verification best practices.

Requirements

• Master’s degree in Computer Science, Computer Engineering, Electrical Engineering, Electronic Engineering, or closely related technical field
• Two years of experience as a Design Verification Engineer or related occupation performing IC design or validation
• Demonstrated expertise in Perl or Python scripting for data processing, data design creation, data collection, analysis, design automation tools controls, and input/output data formatting
• Demonstrated expertise executing the full-lifecycle of design/verification, including verification planning, test bench and test case development, architecting coverage and performing system debugging utilizing Cadence Xcelium simulator suite, Synopsys VCS or equivalent
• Demonstrated expertise driving metric-driven verification, including specifying, developing, and leveraging advanced verification capabilities using System Verilog, UVM, and coverage analysis
• Demonstrated understanding of analog and digital circuits through prior work experience and coursework
• Demonstrated expertise eliciting and communicating complex technical details before key stakeholders

Benefits

• Medical, vision and dental coverage
• 401k
• Paid vacation
• Holidays
• Sick time