Staff Engineer, Design Verification Engineering

Analog Devices is seeking a Staff Design Verification Engineer to contribute to the design verification of impactful and innovative analog and mixed-signal products and technologies. The successful candidate will join a talented and motivated multi-disciplinary team, collaborating with internal technology groups and external technology vendors to establish and continuously improve a best-practice development methodology for the team.

Requirements

• Bachelors/Master's degree in electronics engineering or equivalent with 7+ years of experience
• Contributions to full chip level design verification of mixed signal devices
• IC top-level DMS SV/UVM verification, Object-Oriented and Randomized Verification, as well as Gate Level Simulation
• Top-level metric-driven analog mixed-signal (AMS) simulations
• Modelling and validation of analog blocks (RNM, Verilog-AMS)
• Proficiency with Cadence tool suite, such as Xcelium/IMC/Virtuoso etc.
• Verification planning tools (ePlanner/vManager) and scripting languages (Shell/TCL/Perl/Python)
• An understanding of FPGA prototyping/tools, and supporting development of necessary scripting and pre-silicon validation
• Experience with multiple clock and power domains
• Strong verbal and written communication skills and ability to collaborate with a global team

Benefits

• Equal opportunity employer