Apple is committed to inclusion and diversity and seeks to promote equal opportunity for all applicants.
This CPU Gate Level Synthesis Engineer will drive the early-stage development of high-performance, low-power CPUs. The role involves running RTL to gate-level synthesis, optimizing timing, power, and area for micro-architectural features, and collaborating with cross-functional teams. Responsibilities include RTL health assessment, power estimation, DFT integration, and feedback analysis.
Apple is committed to inclusion and diversity and seeks to promote equal opportunity for all applicants.