Arteris

10+ years of accounting experience, US GAAP knowledge, leadership skills, and Excel competence required

8 years of experience in cache coherency verification and validation, with a strong understanding of cache hierarchies and their interaction with NoC interconnects

Internship, technical documentation, migration, Confluence, attention to detail, written communication

Defining, optimizing, and evolving cache coherency solutions and developing cutting-edge cache-coherent interconnect IP

4+ years of industry experience, strong understanding of hardware RTL design and verification languages, and experience in verification methods and infrastructure

Must have >5 years' experience in front-end System LSI design, be highly motivated, and have excellent problem-solving skills

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field; Proven experience as a Cache Coherency Architect, Design Engineer, or similar role; Strong understanding of SoC and NoC architecture, cache coherency protocols, and memory hierarchy

7+ years of experience as RTL verification engineer, UVM framework expertise, and proficiency in Python scripting language

Bilingual French/English, Microsoft Office suite, and excellent interpersonal skills

3+ years’ experience on SoC, system on chip, IPs integration or IP RTL design, with strong emulation experience working on available platforms