Chip Architect

Astera Labs is seeking a Senior Principal Chip Architect to lead the architectural definition of next-generation ASIC solutions targeting hyperscale data centers. The role involves driving technical decision-making, product lifecycle ownership, and technical leadership.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Science, or related technical field
• 12+ years of proven success as an ASIC/Chip Architect or System-Level Integrator at semiconductor companies
• Demonstrated background in networking domain with deep familiarity with Ethernet standards
• Proven track record delivering complex hardware designs from high-level definition through successful tapeout and high-volume production
• Strong communication and interpersonal skills with ability to influence cross-functional teams
• Experience making architectural trade-offs balancing power, performance, area, and cost

Benefits

• Competitive salary
• Stock options
• Health insurance
• Retirement plan
• Generous parental leave