Design Engineer

Astera Labs is seeking a Senior VLSI Design Engineer to help build their local engineering powerhouse in Israel. The role involves designing complex digital blocks for AI infrastructure connectivity projects. The team defines the next generation of AI infrastructure main components and the candidate will own the journey from high-level definition through RTL implementation and backend support.

Requirements

• Bachelor's degree in Electrical Engineering or related technical field
• 3+ years of experience in logic design at semiconductor companies
• Knowledge and experience in Verilog and/or SystemVerilog
• Excellent communication skills with ability to work effectively across teams
• Understanding of digital design principles and RTL coding best practices

Benefits

• Competitive salary and benefits package