Senior Design Verification Engineer

Astera Labs is seeking a Senior Design Verification Engineer to join our team. The ideal candidate will play a key role in verifying the functionality and performance of our digital and mixed-signal designs.

Requirements

• Bachelor’s in Electrical Engineering, Computer Engineering, or a related field.
• 2+ year of experience in DV.
• Strong proficiency in verification languages such as System Verilog, UVM (Universal Verification Methodology).
• Experience with simulation tools (e.g., Cadence Xcelium, Synopsys VCS, or Mentor Graphics QuestaSim).
• Familiarity with scripting languages such as Python, Perl, or Shell scripting for automation purposes.
• In-depth understanding of digital design principles, verification methodologies, and industry-standard protocols.
• Excellent analytical, debugging, and problem-solving skills.
• Strong teamwork and communication abilities.

Benefits

• Competitive salary.
• Performance bonus each year.
• Flexible working time.
• Health check each year.
• Insurance for engineer and family.
• Lunch Allowance.
• Company trips.