Senior Silicon Validation Engineer

Astera Labs is looking for motivated Senior / Tech Lead Post-Silicon Validation Engineers to work on their game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications.

Requirements

• Strong academic and technical background in Electrical or Computer Engineering.
• At least 3 years' experience testing, supporting or developing complex SoC/silicon products and high-speed IO/SerDes electrical interface for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for internal meetings in advance, and to work with minimal guidance and supervision.
• Proven track record solving problems independently, preferably as a tech lead.
• Experience working on debug and bring-up of complicated SoC's with high-speed interfaces such as PCIe/802.3x Ethernet.
• Strong problem-solving skills, ability to solve problems independently.
• Basic knowledge of key, high-speed design blocks such as PLL's, CTLE, DFE, Tx EQ, and both NRZ and PAM4 signaling.
• Strong python scripting and coding ability: knowledge of object-oriented programming and basic dev ops using git for source control and collaboration.
• Proficiency using high-speed lab equipment such as BERT, Oscilloscope, and VNA