Senior Engineer - Silicon Physical Design (Italy based)

As a Senior Silicon Physical Design Engineer at Axelera AI, you will play a crucial role in developing cutting-edge multi-core in-memory compute SoCs. Leveraging your expertise in ASIC Physical Design from RTL to GDS, you will be responsible for synthesis, floorplanning, place and route, extraction, timing analysis, physical verification, EMIR signoff, and formal verification.

Requirements

• 10+ years of experience in Physical Design (RTL to GDS)
• Strong communication and teamwork skills
• Expertise in synthesis, timing analysis, and timing closure
• Hands-on experience with leading EDA tools (Primetime, StarRC, Genus, Innovus, Design Compiler, ICC/ICC2, FC, and Calibre)
• Proficiency in clocking techniques and CTS
• Experience in IP integration across various domains
• Strong scripting skills (Python, Tcl, or Perl)
• Proven problem-solving and debugging capabilities
• Fluent in English (spoken and written)

Benefits

• Attractive compensation package
• Pension plan
• Extensive employee insurances
• Option to get company shares