Senior Staff ASIC Design Engineer

Axiado is seeking a Senior Staff ASIC Design Engineer to help develop the design and implementation/integration of SoCs. The ideal candidate will have 12+ years of experience in RTL logic design, verification, synthesis, and timing optimization.

Requirements

• 12+ years of experience in RTL logic design, verification, synthesis, and timing optimization
• Proficient in writing clear, implementable micro-architecture specifications
• Expertise in writing efficient RTL code in Verilog and SoC integration
• Good understanding of assertions, coverage analysis, RTL synthesis, and timing closure
• Should have worked on interface protocols like PCIe, USB, Ethernet, DDR/LPDDR4/5, I2C/I3C, eSPI, SPI, etc.
• Experience in design bring up and debug on FPGA based emulation platforms like HAPS, Veloce
• Fluency with scripting languages (e.g., Perl, Python)
• Must have gone through at least one complete tape-out cycle