Senior RTL Design Engineer

Design and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators.

Requirements

• 8+ yrs of recent industry experience in high-performance, energy-efficient CPU designs.
• Expertise in CPU processor designs in one or more of the following areas: instruction fetch and decode; branch prediction; register renaming and instruction scheduling; scalar and/or vector execution units; load-store unit; cache and memory subsystems.
• Proficiency with hardware (RTL) design in Verilog, System Verilog, or VHDL.
• Knowledge of at least one object-oriented and/or functional programming language.
• Background of successful CPU development from architecture through tapeout.