Design for Test Engineers

We are looking for skilled and motivated Design for Test (DFT) Engineers with 4–10 years of experience in developing and implementing advanced DFT methodologies for complex SoCs and ASICs.

Requirements

• Develop and implement DFT architectures for SoC/ASIC designs.
• Utilize expertise in Scan Insertion, ATPG, MBIST, LBIST, JTAG, and Boundary Scan.
• Work on tool flows for Synopsys/Mentor/Cadence DFT tools.
• Collaborate with RTL, physical design, verification, and test teams to integrate and validate DFT features.
• Debug and resolve issues during synthesis, simulation, and silicon bring-up.
• Deliver high-quality test coverage while optimizing for area, power, and performance impact.
• Support ATE patterns generation and silicon validation.

Benefits

• Competitive salary and performance-based bonuses.
• Health, dental, and vision insurance.
• Retirement plan with employer matching.
• Paid time off and holiday leave.
• Ongoing training and professional development opportunities.