Sr Staff DFT Engineer (AI2435)

The Sr Staff DFT Engineer will be responsible for developing and executing test insertion flow for scan, MBIST, JTAG, and estimating and achieving targeted test coverage. The ideal candidate will have in-depth knowledge of VLSI design and hardware description languages such as Verilog, as well as experience with complex block-level and SOC-level DFT execution in advanced finFET technology.

Requirements

• BSEE/MSEE or equivalent degree with 7+ years of experience
• In-depth knowledge of VLSI design as well as hardware description languages such as Verilog
• Experience with complex block-level and SOC-level DFT execution in advanced finFET technology
• Deep knowledge with EDA tools such as Synopsys Tetramax or Mentor Tessent
• Good problem solving and debug capabilities
• Good knowledge of hardware simulation tools like VCS, Verdi, etc.
• Proficient in scripting languages (C/C++/TCL/Perl/Python)
• Ability to work with cross functional and cross site teams
• Good communication skills
• Self-driven individual and a good team player