Design Engineer - Chip Floorplanner

Be part of the Custom Silicon Design Team within Broadcom’s ASIC Products Division in beautiful Fort Collins, Colorado. Join a world-class engineering group developing custom CMOS ASICs for cutting-edge AI, Cellular, Networking, Computing, and Storage products.

Requirements

• Define and optimize top-level floorplan architecture, including die size estimation, hierarchy definition, and partitioning.
• Drive macro placement, power grid design, clock distribution planning, pin placement, and feedthrough optimization.
• Collaborate closely with RTL, timing, and packaging teams to balance performance, power, and area (PPA) targets.
• Lead top-level timing closure, congestion analysis, and ECO implementation to ensure clean tapeout readiness.
• Coordinate with block owners and integration teams for smooth block-level to top-level convergence.
• Support cross-functional design integration, providing guidance and technical support to internal and external partners.
• Apply a deep understanding of block PnR, timing closure, physical verification, and IR/EM analysis to achieve signoff-quality results.
• Contribute to design flow automation and methodology development for advanced process technologies.

Benefits

• Medical, dental and vision plans
• 401(K) participation including company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• company paid holidays
• paid sick leave and vacation time