Broadcom is looking for a senior level ASIC physical design engineer to contribute to SerDes connectivity ASICs for highly integrated data center products.
Requirements
- MS in Electrical Engineering or Computer Engineering
- 6+ years of experience in Physical design
- Deep knowledge about industry standards in Physical Design, Physical aware synthesis, Floorplanning, CTS and place and route
- Experience in developing and implementing Power-grid and high speed clock constraints and specification
- Good understanding of physical design verification methodology to debug LVS/DRC issues at the chip and block level
- Experience with CDC, static timing analysis methodologies and relevant tools
- Exposure to SDF annotated simulations with good understanding of parasitic delays
- Understanding and experience of mixed signal environments is a must
- Familiarity with Virtuoso, Caliber & Redhawk (power analysis) tools
Benefits
- Medical, dental and vision plans
- 401(K) participation including company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- company paid holidays
- paid sick leave and vacation time
- Paid Family Leave and other leaves of absence