R&D Engineer IC Design responsible for verification of complex switch designs, creating SystemVerilog-based verification environments, and executing test plans.
Requirements
- Master's Degree in Electrical and Electronic Engineering, Computer Science, or equivalent
- A minimum of 6 years of work experience in Design Verification
- Strong knowledge and hands-on experience in verification methods, tools and environment
- Strong programming skills, including in System Verilog and scripts languages
- Knowledge and experience in UVM methodology is preferable
- Knowledge of networking and switching concept is a plus
Benefits
- Medical, dental and vision plans
- 401(K) participation including company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- company paid holidays
- paid sick leave and vacation time
- Paid Family Leave