Lead Design Engineer

Lead Design Engineer at Cadence, developing & integrating foundry rule decks & technology files to support PDKs, responsible for physical verification methodology and automation, and supporting layout teams in verification flow issues.

Requirements

• Bachelor’s Degree in Electrical/Electronic Engineering or equivalent
• 4-7 years of Work experience in PDK development and CAD enablement
• Expertise in Cadence Python, SKILL, Perl programming languages
• Knowledge of deep sub-micron CMOS processes, device physics and layout design
• Experience with Cadence custom IC Virtuoso platform
• Experience in developing PDK device library components and definitions
• Experience with physical verification tools for DRC, LVS and parasitic extraction
• Working knowledge of revision control software (Git, sos, Subversion, Synchronicity, etc)

Benefits

• We’re doing work that matters. Help us solve what others can’t.