Join Cadence's Digital and Signoff Group (DSG) as a Product Engineer, influencing the next generation of chip design software and helping industry leaders solve complex physical design challenges.
Requirements
- BS in Electrical Engineering (EE) + 4 or more years of industry experience, OR MS in Electrical Engineering (EE) + 2 or more year of digital implementation experience.
- Deep understanding of the full ASIC design flow (RTL-to-GDSII) with a focus on physical design and timing analysis.
- Proven hands-on experience with timing closure and PPA optimization at 7nm, 5nm, or below.
- High familiarity with industry-standard EDA tools for synthesis, placement, routing, and signoff.
- Proficiency in Tcl, Python, or Perl (familiarity with AI-driven productivity tools is a major plus).
- Strong verbal and written skills to translate complex technical issues into actionable solutions.
Benefits
- paid vacation
- paid holidays
- 401(k) plan with employer match
- employee stock purchase plan
- medical, dental and vision plan options