Principal Product Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. This is an exceptional opportunity to become part of the dynamic and expanding Product Engineering team within the DDR IP division at Cadence Design Systems.

Requirements

• Protocol & Physical Layer: Demonstrate a strong understanding of DDR, LPDDR and GDDR implementations.
• Primary Technical Liaison: Act as the main technical contact for debugging customer silicon issues, both for systems and ATE
• Lab Equipment Proficiency: Demonstrate hands-on experience with oscilloscopes, BERTs, protocol exercisers, and analyzers.
• Signal Integrity (SI) and Power Integrity (PI): Understand SI and PI requirements for the IP and assist in diagnosing related hardware issues.
• Onsite Support: Travel to customer sites (about 10% of the time) for bringup and debug of silicon issues.
• Technical Issue Management: Own support cases filed by the customer on SFDC.Use tools such as Sherlock and JIRA to document and coordinate issue debugging.
• AI Incorporation: Leverage AI-powered tools and assistants to enhance productivity, improve decision making, and maintain high-quality customer deliverables. Apply AI-powered analytics tools to extract insights, identify patterns, and generate actionable recommendations from complex datasets.