Software Engineer II

Design and develop cycle approximate/Loosly timed C++/SystemC models for Cadence's IPs, participate in defining traffic patterns and methodology, and develop functional and behavioral models using C++/SystemC/TLM2. Experience in high performance SOC architecture and scripting languages required.

Requirements

• Design and develop cycle approximate/Loosly timed C++/SystemC models
• Participate in defining traffic patterns, tools and methodology
• Develop functional and behavioral (loosly timed)/(cycle-level) models using C++/SystemC/TLM2
• Experience in high performance SOC architecture
• Experience in using RTL/UVM System Verilog simulation environments
• Experience in creating workloads for different SoC components
• Knowledge of scripting languages (python, perl)
• Excellent communication skills and ability to work in a team