Principal SerDes System/DSP Design Engineer

As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact.

Requirements

• Lead the design and development of electrical SerDes DSP architectures for high-speed data communication systems.
• Perform system-level evaluation, modeling, and performance analysis of SerDes transceiver solutions including impairments and mitigation techniques.
• Develop algorithms and architectures for adaptive equalization, maximum likelihood sequence detection (MLSD), and timing recovery algorithms.
• Collaborate with cross-functional teams (analog design, ASIC design, electro-optical hardware, firmware) to optimize SerDes performance in end-to-end systems.
• Conduct design trade-offs to meet stringent performance, power, and area targets.
• Analyze channel models, analog circuits impairments (DAC, ADC, AFE,...) and system constraints to determine system level margin and FEC (forward error correction) performance and optimize system margin.
• Provide system level specifications for different sub-blocks of SerDes transceivers such as DAC, ADC, AFE, PLL.
• Evaluate and model IMDD optical links and formulate strategies to enhance system robustness.
• Document design specifications, system performance results, and contribute to IP generation and innovation roadmaps.

Benefits

• Medical, dental, and vision plans
• 401(K) (USA) & DCPP (Canada) with company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• Company-paid holidays
• Paid sick leave
• Vacation time