Senior ASIC Synthesis and STA Engineer
CienaOttawa, Ontario, Canada
Posted February 26, 2026
109000 - 174000 CAD
Full Time
About the Company
Ciena (NYSE:CIEN) is the global leader in high-speed connectivity. We build the world’s most adaptive networks to support exponential growth in bandwidth demand. By harnessing the power of our networking systems, components, automation software, and services, Ciena revolutionizes data transmission and network management. With unparalleled expertise and innovation, we empower our customers, partners, and communities to thrive in the AI era.
Job Description
Ciena is seeking a Senior ASIC Synthesis and STA Engineer to join its team. As a key contributor to the company's next-generation Wavelogic Digital Signal Processor (DSP) programs, the successful candidate will be responsible for executing frontend implementation, developing timing constraints, and collaborating with cross-functional teams.
Requirements
- B.Sc. in Electrical Engineering, Computer Engineering, or a related discipline (or equivalent experience)
- Industry experience using synthesis and/or static timing analysis tools within an ASIC development environment
- Knowledge of ASIC implementation flows, including synthesis, timing analysis, logical equivalence checking, and clock domain crossing validation
- Familiarity with RTL design principles and hardware description languages
- Ability to work effectively within multidisciplinary engineering teams and manage deliverables to project schedules
Benefits
- Comprehensive benefits package
- 401(K) (USA) & DCPP (Canada) with company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- Paid holidays
- Paid sick leave
- Paid vacation time
- Paid Family Leave