ASIC Engineering Lead

Role Overview

Join Cisco's CHG Team in Armenia to lead the end-to-end physical implementation of high-complexity silicon blocks from RTL to tape-out. Collaborate with global teams to resolve complex implementation challenges and ensure seamless system-level integration.

What You Will Do

Lead the physical implementation of high-complexity silicon blocks, apply expertise in synthesis, place-and-route, and timing closure, and provide technical direction to peers.

Why It Might Be a Fit

This role requires a strong background in ASIC design, physical implementation, and verification, with a proven ability to mentor team members and foster a collaborative environment.

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field
• Minimum of 8 years of experience in ASIC design, physical implementation, and verification
• Proven expertise in deep submicron CMOS technologies
• Extensive knowledge of the full design cycle from RTL to GDSII
• Demonstrated mastery in block-level synthesis, place-and-route, and timing closure
• Excellent verbal and written communication skills in English

Benefits

• Collaborative environment
• Opportunities for growth and development
• Global team collaboration
• Meaningful solutions
• Unparalleled security, visibility, and insights