[India] Senior ASIC Implementation Engineer

We are seeking a highly skilled Senior ASIC Implementation Engineer to join our team. The successful candidate will be responsible for a range of key ASIC implementation tasks, including but not limited to synthesis, timing constraints, implementing ECOs, STA, Power intent implementation & validation, lint, power analysis, CDC RDC Analysis & Validation.

Requirements

• Professional ASIC hardware design and/or implementation experience.
• Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power.
• Debug the timing/area/congestion issues in physical implementation and work with RTL & Physical desig teams to resolve them
• Perform Power Estimation at RTL and Gate Level and identify power reduction opportunities
• Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures
• Perform RTL Lint and work with the Design team to create waivers
• Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC
• Develop Power Intent Specification in UPF for the multi-Vdd designs.
• Use Conformal ECO flow, and able to implement complex large ECOs
• Take a part in PD activities from floor planning to P&R

Benefits

• Competitive compensation package
• Comprehensive paid time off, vacations and sick leaves