[Japan] Design Verification Engineer

We are looking for an experienced and motivated Design Verification Engineer to join our Artificial Intelligence Hardware Accelerator Team at EdgeCortix. You will collaborate closely with our design and architecture teams to build and enhance advanced verification environments for our next-generation AI SoCs.

Requirements

• 6-7 years of experience in functional verification of blocks/systems using SystemVerilog/UVM
• Strong understanding of verification techniques including assertions, metric-driven and coverage-driven verification
• Experience in developing full verification infrastructure from scratch
• Experience with verification of systems which involve high-speed buses such as AXI4
• Experience with gate level simulations and delay modeling
• Experience with constraint random verification
• Experience with writing functional coverage and overall code coverage analysis
• Experience with coverage-driven verification methodology
• Experience in writing and debugging System Verilog assertions
• Strong experience in debugging RTL and testbenches

Benefits

• Highly competitive salary
• Stock options
• Flex work time
• Ability to work fully remotely
• Support for obtaining a visa
• Relocation support