ASIC Chip Design Lead

Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions for large-scale AI models. We are seeking a hands-on ASIC Chip Design Lead to own chip design execution from micro-architecture through full-chip integration and timing signoff.

Requirements

• Strong hands-on experience with RTL design and micro-architecture
• Proven experience with full-chip integration and timing closure
• Led at least one full-chip tape-out within the last 3 years, with direct responsibility for design signoff and PD handoff
• Deep understanding of synthesis, static timing analysis, and physical-design collaboration
• Experience refactoring and restructuring RTL to resolve timing, area, and congestion challenges
• Comfortable working cross-functionally with architecture, verification, firmware, and physical design teams
• Demonstrated ability to drive execution in ambiguous, fast-moving environments