RTL Design Engineer

Etched is building AI chips that are hard-coded for individual model architectures. As an RTL Engineer, you will develop and implement design verification strategies for both existing and upcoming ASIC designs, working closely with state-of-the-art architectures for machine learning.

Requirements

• At least 5 years of work experience in RTL development.
• Experience with high-speed digital logic.
• Proficiency in standard RTL design and synthesis tools
• Familiarity with verification work and writing test benches

Benefits

• Full medical, dental, and vision packages, with 100% of premium covered, 90% for dependents
• Housing subsidy of $2,000/month for those living within walking distance of the office
• Daily lunch and dinner in our office
• Relocation support for those moving to Cupertino