Graphcore is expanding its teams around the world to meet the vast and exciting AI opportunity. We are bringing together the brightest minds to solve the toughest problems in a place where everyone has the opportunity to make an impact on the company, our products, and the future of artificial intelligence.
Requirements
- Very good understanding of DFT components like JTAG (IEEE 1149.x), IJTAG (IEEE P1687), Core Test (IEEE P1500), SSN (Streaming Scan Network), Test Compression, OCC etc.
- Experience on developing DFT specifications and driving the implementation of the DFT features
- Experience in MBIST and BISR implementation and verification is desired
- Solid understanding of design verification methodologies for validating the DFT features using simulation in pre-silicon designs
- Exposure to STA constraints development and analysis for DFT modes and SDF simulations would be a plus
- Experience in Scan based testing and industry standard ATPG tools
- Knowledge of ATPG pattern verification and gate-level simulation flows using Synopsys VCS and Verdi or other EDA tools
- Very good knowledge of Digital Integrated Circuits and Systems
- Hands-on experience with Verilog RTL coding and familiarity with System Verilog
- Strong scripting and debugging skills using programming languages like Python, TCL, Perl, Shell etc.
- Exposure to silicon bring-up, post-silicon testing and tester pattern debugging
- Strong problem-solving skills across various levels of design hierarchies
- Great team working and communication skills
Benefits
- Flexible working
- Generous annual leave policy
- Private medical insurance and health cash plan
- Dental plan
- Pension (matched up to 5%)
- Life assurance and income protection
- Generous parental leave policy
- Employee assistance programme (which includes health, mental wellbeing, and bereavement support)