HIring for ASIC verification

Happiest Minds is hiring for ASIC verification engineers with 5-8 years of experience. The ideal candidate will have knowledge of high-level verification languages, FPGA design, and development flow. The role involves implementing verification environments, understanding and improving existing verification flows, and contributing to methodology development.

Requirements

• Knowledge of high-level verification languages like System Verilog
• Experience with OVM/UVM methodology and Synopsys VCS/Mentor Questa
• Understanding of FPGA design and development flow
• BE/B Tech/ME/M Tech degree in Electronics