We're searching for a forward-thinking Senior FPGA Design Verification Engineer to help us build the future of capital markets infrastructure.
Requirements
- BS/MS in Computer Engineering, Electrical Engineering, Computer Science, or related
- 5+ years of experience in design verification for FPGAs or ASICs
- Proficiency in SystemVerilog for verification
- Familiarity with advanced verification methods, including constrained randomization, functional coverage, and assertion-based checking
- Experience with industry-standard simulation and debugging tools (e.g., VCS, Verdi)
- Comfortable working in a Linux environment
- Strong problem solving, debugging, and communication skills
Benefits
- Opportunity to work with cutting-edge technology
- Chance to contribute to improving verification processes, tools, and methodologies
- Collaborative and continuous learning culture