Design Verification Engineering Manager

Intel is seeking a highly qualified candidate to lead a chiplet verification team in a dynamic and forward-thinking organization focused on next-generation semiconductor product development.

Requirements

• Bachelor's degree in electrical engineering, computer engineering, computer science, or in other relevant STEM related degree.
• 6+ years of experience in ASIC/FPGA design verification
• Strong understanding of object-oriented programming (OOP) principles and their application in SystemVerilog UVM or other verification methodologies.
• Developing UVM and/or Formal based verification architectures and methodologies.
• Experience with industry standard protocols (AMBA AXI/AXI-S/CHI and communication protocols (e.g., PCIe, Ethernet, UART, SPI, I2C/I3C))
• Hands-on experience with simulators (Synopsys VCS, Cadence Xcelium, or equivalent).
• Familiarity with coverage-driven verification, constrained-random testing and strong debugging skills.
• Experience with scripting languages.

Benefits

• Competitive pay
• Stock bonuses
• Health benefits
• Retirement benefits
• Vacation benefits