Senior Design Verification Engineer

Intel is seeking a Senior Design Verification Engineer for the Silicon Chassis team to own verification planning and execution for assigned IP blocks and features at IP and subsystem level, drive test plans through coverage closure, and collaborate closely with architecture, design, and software teams.

Requirements

• BS/MS in Electrical Engineering, Computer Science, or related field
• 8-12 years of relevant experience in design verification
• Strong background in IP-level DV with meaningful exposure to subsystem-level verification
• Strong expertise in interconnects and bus protocols
• Strong background in simulation-based verification methodologies
• Hands-on coding proficiency across SystemVerilog/UVM, C/C++, and Python

Benefits

• Generous Paid Time Off
• 401k Matching
• Retirement Plan