SoC/IP Design Verification Engineer

We're looking for a hands-on SoC Design Verification Engineer to drive verification for complex SoC/IP blocks. You will own verification planning, UVM testbench development, test content creation (directed and constrained-random), coverage closure, and debug across block, subsystem, and SoC levels.

Requirements

• BS/MS in Electrical/Computer Engineering or related field
• 5+ years of SoC/IP design verification experience
• Strong UVM/SystemVerilog development expertise
• Test planning experience
• Proven debug skills in simulation/emulation
• Coverage-driven verification
• Scripting proficiency (Python, Perl, Shell, Make/CMake)