SOC Physical Design Static Timing Analysis Engineer

As a Physical Design Timing Engineer, you will play a pivotal role in shaping the performance, power efficiency, and functionality of Intel's cutting-edge System-on-Chip (SoC) designs. You will perform SOC level timing analysis and optimization, generate and verify timing constraints, and develop optimized clock networks for functionality, performance, and power efficiency. You will also collaborate with multiple teams to enhance efficiency and operational excellence.

Requirements

• Perform SOC level timing analysis and optimization
• Generate and verify timing constraints
• Develop optimized clock networks for functionality, performance, and power efficiency
• Conduct timing rollups
• Establish PVT conditions for timing analysis

Benefits

• Competitive pay
• Stock bonuses
• Health benefits
• Retirement benefits
• Vacation time