We are seeking a Principal Engineer DFT to transform how the world uses information to enrich life for all. The ideal candidate will have 10+ years of experience in SoC design, DFT, or implementation for sophisticated digital ASICs or SoCs.
Requirements
- Own DFT implementation, including scan, MBIST, LBIST, boundary scan, and test access architectures for mixed signal SOC’s/ designs.
- Drive DFT architecture definition early in the design cycle, ensuring alignment with SoC integration, floor planning, timing, power, and physical design constraints.
- Implement and integrate DFT logic at the block, subsystem, and full-chip levels, working closely with RTL and integration teams.
- Own DFT flow execution and signoff, including lint, CDC, DFT rule checks, ATPG readiness, and coverage closure.
- Collaborate with physical design teams to ensure DFT solutions are optimized for placement, routing, timing closure, and DRC/LVS signoff.
- Work closely with verification, product engineering, test, probe, and manufacturing teams to ensure testability, diagnosability, and smooth silicon bring-up.
- Support pre-silicon debug of DFT-related issues and assist with post-silicon bring-up and yield/debug analysis.
- Partner with CAD and methodology teams to define, improve, and standardize DFT flows across Analog-Mixed Signal SoC programs.
Benefits
- Paid Time Off
- 401k Matching
- Retirement Plan
- Generous Parental Leave
