R&D Intern - FPGA/RTL Design Engineer - 2026

The R&D Intern - FPGA/RTL Design Engineer will report to the Senior Engineering heading our Irvine Engineering team and contribute to the development of Silvus advanced research projects.

Requirements

• Working with system engineers and digital design architecting for wireless communication projects.
• RTL coding, simulation, and test bench development.
• FPGA synthesis and timing closure.
• Hardware verification and troubleshooting.
• Demonstrated experience with fixed point binary arithmetic and digital signal processing designs.
• Knowledge of RTL design fundamentals using Verilog/VHDL.
• Experience with Xilinx FPGAs, SoCs, and the Vivado IDE.
• Must be a U.S. Citizen due to clients under U.S. government contracts.
• All employment is contingent upon the successful clearance of a background check and drug testing.