DFT Engineer

Design-for-Test Engineer role at NVIDIA involves crafting creative solutions for DFT architecture, verification, and post-silicon validation on complex semiconductor chips. Responsibilities include design and implementation of state-of-the-art designs, verification, and silicon bringup of DFT features. The role requires collaboration with multi-functional teams, occasional travel, and late hours online meetings.

Requirements

• BSEE or MSEE from reputed institutions or equivalent experience.
• 2+ Years of experience preferably in Design for testability (DFT).
• Well versed with static timing Analysis, ECO, ASIC/Logic Design Flow, HDL and Digital logic design.
• Experience in RTL and Gates verification and simulation.
• Familiar with BIST architecture and JTAG/IEEE1149.1/IEEE1500.
• Strong DFT knowledge in Scan ATPG, compression techniques and memory test.
• Strong analytical and problem solving skills.
• Expert coding skills in industry standard scripting languages.
• Extraordinary written and oral communication skills with the curiosity to work on rare challenges.