Senior Logic Design Engineer, Cache Coherent Interconnects

We are now looking for a Senior Logic Design Engineer to join our CPU Logic Design Team. As a member of this team, you will be responsible for the design of CPU on-chip and off-chip interconnect network, MP coherency and last-level and system caches, focusing on such tasks as micro-architectural definition, RTL coding, logic debug, synthesis and timing closure, supporting verification and implementation.

Requirements

• Master’s Degree in Electrical Engineering, Computer Engineering or Computer Science or equivalent experience.
• 5+ years of experience in processor or other related high performance semiconductor designs.
• Verilog expertise required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.
• Strong communication and interpersonal skills are required along with the work in a dynamic, global team.
• Your successful track record of mentoring junior engineers and interns a huge plus.
• A strong background in computer architecture, cache coherency or high speed interconnects is helpful.

Benefits

• Eligible for equity
• Benefits