Principal Analog Design engineer

Analog Designer with 12 to 18 years of experience in High speed design which includes Automotive Ethernet and SerDes blocks, responsible for transistor level design, analog circuit characterization/validation, and yield improvement.

Requirements

• 12+ years of Analog experience in high speed design of ethernet/SerDes blocks
• B.E/MS in Electronics/electricals Engineering
• Transistor level design knowledge and experience of standard analog building blocks including Bandgap references, current references, OPAMP, LDO, receiver front-end blocks PGA, CTLE and such for ultra-low noise performance in CMOS processes
• Experience with relevant CAD tools (including Cadence Virtuoso, SPICE, etc.)
• Experience on solving Product level EMC/ESD issues
• Proficient with using analog circuit design EDA tools such as Cadence ADE
• Have knowledge of basic transistor models (CMOS)
• Experience with Analog circuit characterization/validation, Yield improvement, ATE characterization etc.
• Experience on Multi-gig ethernet is a plus