SoC Digital Physical Design Engineer - MCU

NXP is hiring a SoC Digital Physical Design Engineer - MCU in Catania. The role will lead the physical design implementation of complex, high-performance integrated circuits, from RTL to GDSII. The candidate will drive advanced methodologies, mentor and develop junior engineers, and contribute to the successful tape-out of cutting-edge MCU SoC designs.

Requirements

• Master's degree in Electrical Engineering, Electronics Engineering, VLSI Design, or a related field.
• Working knowledge on advance tech nodes 16ff and below is highly desirable.
• Expert-level proficiency with industry-standard EDA tools from Synopsys (Fusion Compiler, ICC2, Primetime, Design Compiler), Cadence (Innovus, Tempus, Genus), or Siemens (APR, Calibre).
• Deep understanding and practical experience with all aspects of the physical design flow, including floorplanning, power planning, block integration, P&R, CTS, STA, Formal Verification, and Physical Verification.
• Strong expertise in timing closure, including hierarchical STA, AOCV/POCV, multi-corner/multi-mode analysis, and complex timing constraint debug.
• Proven experience in power integrity analysis (IR/EM) and optimization techniques.
• Solid understanding of signal integrity (SI) issues and solutions.
• Proficiency in scripting languages such as Tcl, Python, and Perl for automation and flow development.
• Familiarity with low-power design techniques (UPF/CPF, clock gating, power gating, multi-Vt).
• Excellent problem-solving, analytical, and debugging skills.
• Strong communication and interpersonal skills, with the ability to effectively collaborate with cross-functional teams and mentor junior engineers.
• Prior experience in a technical leadership role, driving projects and influencing technical direction.