Design Verification Engineer

We create a diverse set of world-class products in a friendly and team-oriented atmosphere. We provide an environment of continual learning and growth opportunities and support volunteer & charitable programs. We offer a competitive benefit package and a great place to work.

Requirements

• Define detailed verification plans for blocks and systems
• Lead the verification activities in smaller sub-teams
• Develop SystemVerilog/UVM environments for blocks and top-level SoCs
• Debug functional errors in RTL
• Support younger engineers on their activities
• Programming in Python for automation and in C/C++ for embedded software
• Verification of signal processing components
• 3rd party verification IP deployment

Benefits

• Competitive benefit package
• Great place to work
• Continual learning and growth opportunities
• Support for volunteer & charitable programs