Principal ASIC Design Engineer

onsemi is seeking a seasoned Digital Design Expert to lead a Sub-System for the Treo platform. The ideal candidate will have a strong grasp of digital design principles, expertise in SoC architecture, and proficiency in Verilog/System Verilog.

Requirements

• BE/ME in electronics or related technical field
• At least 7 years of relevant experience in semiconductor product development
• Proven expertise in SoC architecture, IP selection, RTL design and verification
• Strong grasp of digital design principles: FSMs, timing analysis, combinational/sequential logic
• Proficiency in Verilog/System Verilog
• Familiarity with tools: Lint, CDC, RDC, Design Compiler
• Experience with standard interfaces: APB, AHB, AXI, SPI, I2C, DMA
• Design techniques: pipelining, low latency, power optimization
• Experience writing high-quality technical documentation
• Proficiency in scripting languages: Python, PERL
• Experience leading small projects
• Ability to write specifications from high-level requirements
• Understanding of DFT, Functional Safety (FuSa)
• Good analytical skills for debug work needed during verification

Benefits

• Medical and Dental
• 401k Matching
• Retirement Plan
• Stock Options