Staff Verification Engineer

Staff Verification Engineer with solid experience in top‐level and block‐level verification of integrated circuits using SystemVerilog, UVM, and assertion‐based verification.

Requirements

• Create top‐level and block‐level verification test plans
• Drive quality to achieve maximum code and functional coverage targets
• Promote innovation in verification methodologies and technologies
• Ensure full verification coverage of all integrated‐circuit components
• Analyze and debug failures
• Lead projects from the planning phase through mass‐production delivery

Benefits

• Generous Paid Time Off
• 401k Matching
• Retirement Plan
• Visa Sponsorship
• Four Day Work Week
• Generous Parental Leave
• Tuition Reimbursement
• Relocation Assistance