We are seeking a highly skilled Silicon Implementation Engineer with deep expertise in physical design and methodology to develop, build and own tools, flows and methodologies for physical implementation and own physical implementation of floorplan blocks from floorplanning to final signoff.
Requirements
- BS w/ 4+ or MS with 2+ years or PhD with 0-1 year(s) of relevant industry experience in physical design and methodology development
- Demonstrated success in taping out complex silicon designs
- Hands-on experience with block physical implementation and PPA convergence
- Strong coding experience with python, bazel, TCL
- Strong experience building physical design tools, flows and methodologies
- Strong understanding of microarchitecture, RTL design, physical design, circuit design, physical verification and timing closure.
- Deep familiarity with industry-standard tools and flows for physical synthesis, PNR, LEC and power estimation
- Bonus: Experience with AI or HPC-focused chips, Experience with optimizing PPA for high performance compute cores, Hands-on experience with top-level design methodologies
Benefits
- 401k Matching
- Retirement Plan
- Generous Paid Time Off