The Principal Engineer, PCIe Verification will be involved in the functional verification of PCIe controller and PCIe-phy at block, sub-system and MLSoC level. The role requires a full-time, on-site presence in the San Jose, CA office.
Requirements
- BS/MS in EE (Electrical Engineering) or CS (Computer Science)
- 12+ years of experience in functional verification and silicon bring-up/debug
- Very good current working experience of UVM and System Verilog based verification methodology
- Working experience on PCIe protocols Gen4/5
- Working experience on PCIe bring-up and debug on Silicon
- Past working experience on UCIe protocols
- Proficiency in C/C++/Python programming
- Good debug and problem solving skill
Benefits
- Generous Paid Time Off
- 401k Matching
- Retirement Plan
- Health Insurance
- Dental Insurance
- Vision Insurance
- Life Insurance
- Disability Insurance